>>>>> + ahci_tegra_port_info.flags |= ATA_FLAG_NO_DIPM; >>> >>> Looking at the downstream device trees, it looks like DIPM and DEVSLP >>> are still disabled for Tegra186 - so why don't we just hardcode these >>> quirks, by always writing the MISC_CNTL_1_0 register and just adding >>> ATA_FLAG_NO_DIPM to ahci_tegra_port_info's static definition. >>> >> >> For Tegra186 the devslp pin is shared with PCIE clk req pin. >> In downstream PCIe driver by default assumes that CLKREQ is present and it >owns it. >> So by default devslp is disabled. We verify devslp by making sure that >> pcie does not own this pin. This issue will be fixed in future chips. > >Ok. How about DIPM, can we hardcode that? If not, or if it is fixed in Xavier, I >think it would be cleaner to have two static port_info structs and select between >then based on the quirk, so that we don't need to mutate the static data. > No, DIPM is not fixed in that chip as well. I will hardcode it now and in future when it gets fixed we can have two port_info structs as suggested. -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
