On Mon, Oct 24, 2016 at 8:16 AM, Christoph Hellwig <hch@xxxxxx> wrote: > On Mon, Oct 24, 2016 at 10:46:29AM -0400, Keith Busch wrote: >> Amber is aware of this and was supportive in having Intel open the >> specs to enable this hardware. > > Ok, let's get the spec out first. The patch contents are it. > Do we expect to be able to use the > AHCI interface and the NVMe interface at the same time? Yes, simultaneous access. > If the first is the case I think we are royally screwed and I see no good way to > support this beast. I'm new to the NVMe driver and spec so I'll tread carefully here... Resets do present a problem especially since they are specified to reset pci registers that we do not have access to read/write. That said, the driver seems to already comprehend instances where the device does not support nvme_reset_subsystem() requests. I don't know how often those resets need to be issued in practice. > If it's the latter let's keep AHCI entirely out > of the game - add the affected PCI IDs to the NVMe driver itself, add > a quirk for them and implement the enable sequence inside the NVMe > driver. The PCI ID of the AHCI device is not uniquely identifiable when in this mode. We could flip the arrangement and have the ahci device as the platform device, but I'm not sure this makes the nvme reset problem much better. If we allow subsystem resets at all they would still need to be coordinated across 2 devices/drivers to reinitialize pci registers. -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
