On Sun, Oct 23, 2016 at 06:57:41AM -0700, Dan Williams wrote: > I should clarify that these are not new devices for the NVMe technical > working group to consider. They are discrete / typical / off-the-shelf > NVMe devices from any vendor. It's just the memory bar and interrupt > vector that are arranged to be shared with an ahci pci device. But this has a profound effect on the NVMe operation, because fo example the NVMe reset cycle is tied into PCIe function states. Please bring this issue up with the relevant standards comittee first, otherwise we're getting us into a nightmare of undefined behavior here. And it's not like Intel isn't active in this group. I'd suggest you talk to Amber who is the editor for both the AHCI and NVMe spec, that should get you started. -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
