On Tue, Feb 16, 2016 at 03:13:32PM -0800, Tirumalesh Chalamarla wrote: > On 02/16/2016 01:14 PM, Robert Richter wrote: > >CONFIG_CAVIUM_ERRATUM_22536 is exactly that you need. It is not only > >used for core interrupts, e.g. also for gicv3 devices (and now also > >for ahci). Non-core errata (e.g. CONFIG_CAVIUM_ERRATUM_23144) are not > >enabled in the arm64 cpu errata framework (not handled in > >arch/arm64/kernel/cpu_errata.c). > > > >Thus, > > > >#ifdef CONFIG_CAVIUM_ERRATUM_22536 > > if (pdev->vendor == 0x177d && pdev->device == 0xa01c) > > ahci_thunderx_init(&pdev->dev, hpriv); > >#endif > > > >is the correct enablement of the workaround by device id. > > > >And, CAVIUM_ERRATUM_* is very easy to handle, enable and document. > > > The code will only run for Thunder and AHCI, becuase its PCI. Well, the guards also serve as documentation for exactly why we're having to do something special here, so I'd say go ahead and add CONFIG_CAVIUM_ERRATUM_22536 and update Documentation/arm64/silicon-errata.txt accordingly. Will -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
