Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> writes: >> > 4. CHECK: PROTCTL bit (documentation says that recommended value is >> > 0x01) >> >> Any idea what the value of 0x3 used by the old sata driver means? >> Presumably that's decided by the bus. > > Nope, documentation says that it is direct representation of hprot[3:1] > wires on the master interface. Also it refers to AMBA spec, so, if you > have access to AMBA spec I think we might get it from there. That's assuming AMCC didn't change something. >> > 5. CHECK: Other bits in CFG register (FIFO_MODE, FCMODE) >> > 6. CHECK: Block interrupts vs. one interrupt at the end of block >> > chain >> > (Måns, I missed how any of them is ignored) >> >> The interrupt handler looks at the StatusTfr and StatusErr registers >> and ignores StatusBlock. > > I have to refresh my memory, since BLOCK interrupts should be enabled > (unmasked) separately. I have forgotten which type of interrupt is > generated in this case, BLOCK, or XFER after each block, or only one > XFER at the last block (LLP.LOC = 0) and BLOCK are ignored. So, will > check later. I interpreted the, admittedly a bit vague, documentation as meaning BLOCK interrupts are signalled after each block and XFER interrupts after the last block. >> > 7. AR: Test everything on Intel SoCs such as Baytrail, CherryTrail, >> > etc (SPI, UART, dmatest), AVR32 (MMC, dmatest), PPC 460EX (Onboard >> > SATA) >> >> I can test on AVR32. That is as far as I know the only system I have >> with this DMA engine. > > If you have Intel Haswell, BayTrail, Braswell, CherryTrail, Broadwell, > you have it as well as long you have LPSS block there. (Most of them > are Atoms). I don't have any of those (or any Atom hardware). -- Måns Rullgård -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
