Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
Cc: Shawn Guo <shawn.guo@xxxxxxxxxx>
Cc: Richard Zhu <r65037@xxxxxxxxxxxxx>
Cc: Tejun Heo <tj@xxxxxxxxxx>
Cc: Linux-IDE <linux-ide@xxxxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/clock/imx5-clock.txt | 1 +
arch/arm/mach-imx/clk-imx51-imx53.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 3716b36..8904731 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -199,6 +199,7 @@ clocks and IDs.
spdif_ipg_gate 185
ocram 186
sahara_ipg_gate 187
+ sata_phy 188
Examples (for mx53):
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 3d91172..06bfb4c 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -122,7 +122,7 @@ enum imx5_clks {
srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
- ocram, sahara_ipg_gate, clk_max
+ ocram, sahara_ipg_gate, sata_phy, clk_max
};
static struct clk *clk[clk_max];
@@ -588,6 +588,7 @@ static void __init mx53_clocks_init(struct device_node *np)
clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
+ clk[sata_phy] = imx_clk_fixed_factor("sata_phy", "usb_phy1_gate", 1, 1);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
--
1.8.4.2
--
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