On 04/13/2012 03:18 AM, Thang Nguyen wrote:
Thanks Jeff and Sergei, As your suggestion, I will separate the patch into smaller patches and support more features on the SATA DWC driver. The patches I intend to do on the SATA DWC are as below: - Support hardreset: currently the hardreset is not supported. This causes sometime the SATA driver does cause kernel crash because of not-determined state. - Let device tree specified DMA channel: currently only channel 0 is supported (number of channel is set to 1). If device tree not specified DMA channel, channel 0 will be used as default. - Support ATAPI. - Remove dma_interrupt_count. for each DMA transfer, we need 2 interrupts for QC completion: transfer completion and DMA transfer completion interrupt. The current code wait for both 2 interrupts occur before calling qc_complete. This will make out-of-sync state when an interrupt lost or when errors occur. The change will process DMA register when DMA transfer complete interrupt occur and call qc_issue when command completion interrupt occur. - Fix NCQ issue and set .can_queue back to ATA_MAX_QUEUE. - Support Port Multiplier. - Support 2 SATA ports on Maui.
Sounds good, thanks for splitting up the patch into smaller pieces. The main goal is that separate logical changes should go into separate patches.
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