From: Bartlomiej Zolnierkiewicz <bzolnier@xxxxxxxxx>
Date: Mon, 18 Jan 2010 18:20:58 +0100
> @@ -189,8 +189,7 @@ int ide_timing_compute(ide_drive_t *driv
> * DMA cycle timing is slower/equal than the fastest PIO timing.
> */
> if (speed >= XFER_SW_DMA_0) {
> - u8 pio = ide_get_best_pio_mode(drive, 255, 5);
> - ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
> + ide_timing_compute(drive, drive->pio_mode, &p, T, UT);
> ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
> }
>
The comment above this code should be changed to match
the new behavior.
I've done that for you when checking this in, as follows:
ide-timings: use ->pio_mode value to determine fastest PIO speed
Use the current PIO mode value instead of the physical maximum one
to determine the fastest allowed PIO for shared PIO/DMA timings.
Affected host drivers: amd74xx and via82cxxx.
[ Update comment to match -DaveM ]
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@xxxxxxxxx>
Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
---
drivers/ide/ide-timings.c | 5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c
index c6053ab..c7a65ee 100644
--- a/drivers/ide/ide-timings.c
+++ b/drivers/ide/ide-timings.c
@@ -186,11 +186,10 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed,
/*
* Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
* S.M.A.R.T and some other commands. We have to ensure that the
- * DMA cycle timing is slower/equal than the fastest PIO timing.
+ * DMA cycle timing is slower/equal than the current PIO timing.
*/
if (speed >= XFER_SW_DMA_0) {
- u8 pio = ide_get_best_pio_mode(drive, 255, 5);
- ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
+ ide_timing_compute(drive, drive->pio_mode, &p, T, UT);
ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
}
--
1.6.5
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