On Tue, Dec 01, 2009 at 03:08:08PM +0900, Tejun Heo wrote:
OK, this got me going, thanks! I couldn't find where AC_ERR_HSM is set, but sata_mv now told me about the IORDY timeout. It seems the IDE<->SATA converter is slower than the internal native SATA HD, but probably (see below) still within spec.In libata-sff.c there are several places which set AC_ERR_HSM. They store the reason why they're setting it using ata_eh_push_desc() but for EH commands those messages aren't printed out (we probably need to fix that). Anyways, can you please conver those to printk's and see which one is setting HSM error?
mv_soc_reset_hc_port() sets EDMA_IORDY_TMOUT to the default value of 0xBC which assumes a 150MHz clock. After setting it to 0xFA (which assumes a 200MHz clock) the device works fine (at least with hdparm -tT).
Clock description for the 88F6281 (the SoC on the OpenRD-Base) is incomplete and/or messy in the published documents (Functional Specifications and Hardware Specifications), so I'm not quite sure what the right value is: - Hardware Specifications defines TCLK/Core clock as 200MHz and SATA clock as 150MHz - stock UBoot (i.e. Marvell version) prints 400MHz for "SysClock" and 200MHz for "TClock" - Functional Specifications says eIORdyTimeout is the "number of system cycles", giving 0xBC for "SysClock == 150MHz"
So depending on what exactly the clock source for the IORDY timeout is, the correct value should be one of: - 0x00BC (150MHz, SATA clock from Hardware Specifications; implying the device is too slow so unlikely as it works fine with other hosts)
- 0x00FA (200MHz, TCLK from Hardware Specifications) - 0x01F4 (400MHz, SysClock from UBoot) CU Sascha -- http://sascha.silbe.org/ http://www.infra-silbe.de/
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