Alan Cox wrote:
Point out the breakage please. The driver has been developed and tested
on non-x86 machine with 66 MHz PCI.
static int init_chipset_hpt366(struct pci_dev *dev)
if (chip_type >= HPT370) {
if ((temp & 0xFFFFF000) != 0xABCDE000) {
it then falls through and gets a 33MHz answer from the tests.
If I stash the MHz answer from boot then it works. So I imagine the boot
time value just needs to be dumped into a static for resume to use.
Ah, that... sure, this test only works at boot if there was no smart
enough BIOS around to save the f_CNT -- then the DPLL gets reprogrammed, and
doesn't reflect the default clock anymore...
Alan
WBR, Sergei
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