Grant Grundler wrote:
On Fri, Apr 25, 2008 at 6:46 AM, Mark Lord <liml@xxxxxx> wrote:
...
But there are just *so many* irq cause / mask registers in these chips,
(one for PCI, one for the host function, and one per-port for EDMA,
plus the SATA SError + mask, ..), that even I was getting confused
while working on the code.
Yeah, it's confusing because most of the bits from one "interrupt"
(quotes explained in the next paragraph) register are rolled up into one bit
and available in another register. It seems like someone thought it
would be more efficient to read one register for all possible "causes"
and then have evidence a second register read is really necessary
(because a bit was set). Unfortunately, the result was the default
programming model as suggested by Marvell asks for at least two
MMIO reads just to find out if any IO completions are pending. 'Nuf said.
Kudos to Mark for figuring out how to reduce that to one MMIO read.
..
Readers may note that the interrupt path (for a real mv interrupt)
currently reads three registers (or four if more than one hc interrupts).
Grant was refering to a plan we have formulated to reduce that to
a single read for the non-error cases. Not currently implemented
in the driver (though there are comments marking where to change it).
I'm leaving those optimizations for after the rest of the EH fixes are completed.
Hopefully within a week or less.
Cheers
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