In the case of PCI (am no big expert on this)- I believe the code allows you to address 32 bits at a time...you can see the the effectve address resource address is some where around 0xea900000 - but, if you have PHYS_64BIT & PTE_64BIT - you get resource_types of 64bits...that you can manipulate accordingly. In the case of the eDMA - its 64bit dma operations - thus, you setup the hi portion (by shifting twice by 16 (you get compiler warnings if you try to shiftg the size of the offset - a bug IMHO)) and thus, can play the game I mentioned below and use the power of the PEX inbound/outbound translation windows to move your data correctly to the appropriate 32 bit location... This game works fine very well for 2.6.11 + kernel - there are a few more tests I need to do (like setting mem=<just below the PEX space> and see if it works correctly...and then try again just a little bit above PEX memory space (> ~0xea900000) - if it works below & doesn't work above - it points to a problem with sata_mv doing some type of operation outside the dma engine that is corrupting memory - Thats another issue how does memory dribble/scribbling (only side affect I can think of if something is going wrong with this translation)? I'll try your 'patch' and see if that has any affect as well (and the associated side-affects...) t ________________________________ From: Mark Lord [mailto:liml@xxxxxx] Sent: Thu 11/15/2007 5:14 PM To: Morrison, Tom Cc: Jeff Garzik; linux-ide@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx Subject: Re: 2.6.23.1 - sata_mv (7042) hang with large file operations Morrison, Tom wrote: > The plot thickens - it looks like it might be some type > of problem interacting with the setup of my 4Gig DDR memory > and how I setup some translation windows in my MPC8548E > > I realized this morning that I have an inbound/ output PEX window > Translation Setup for mapping all from/to PEX bus to outside > the physical 4GIG memory space (i.e.: up at 0xC_xxxx_xxxx). Thus, > all output operations that translation from 0xC_xxxx_xxxx to > the pci 32 bit address of xxxx_xxxx) - and vice versa for for > the inbound. Note: we also have a straight 1:1 translation mapping > as well for the lower 4Gig - so that's why this worked without > the below mentioned change... > > So, I changed the Request & Response Hi Addresses (which were > Being shifted by 32 bits down anyways) and 'OR' that with my > 0xC (so the effective 64bit DMA address is 0xC_xxxx_xxxx (where > Xxxx_xxxx is the effective address). This was what we did to > solve the problem with the Marvel Linux driver that we got from > the Marvel site.... > > This all works just fine with ONLY 2 gig of memory in the system > (and still have these inbound/output pex translation windows), > but fails when I put back the 4 Gig (and the 8Gig) DDR memory. > > Unfortunately, this still hasn't solved the problem though - > so there is something else which I am not seeing? .. I don't know much about how 32-bit PPC deals with memory addresses that are more than 32-bits.. But does this patch have any effect: --- old/drivers/ata/sata_mv.c 2007-10-12 12:43:44.000000000 -0400 +++ linux/drivers/ata/sata_mv.c 2007-11-15 17:12:24.000000000 -0500 @@ -685,7 +685,7 @@ { int rc; - if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { + if (0 && !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); if (rc) { rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
