Fajun Chen wrote:
Since primary channel and secondary channel share the same IRQ, the ISR could be called to service one or both channels. So I would think it's normal to see "irq trap" traces when both channels are in IO operation, correct?
The irq trap code only occurs after a certain number of unhandled interrupts.
I have another question in regard to ata_host_intr() function in libata-core.c. For PIO read/write, the status of interrupt pin was not checked before moving the host state machine. Sil680 spec. recommend checking IDE channel interupt (bit 11 in the IDEx Task File Timing and Config + Status register) though. Could someone explain why interrupt status does not need to be checked for PIO?
Reading the Status register (as opposed to AltStatus) should clear the interrupt condition, on standard hardware.
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