On Tue, 30 Jan 2007 20:40:30 +0300 Sergei Shtylyov <sshtylyov@xxxxxxxxxxxxx> wrote: > Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1 > only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly. Thanks for all this review work > Frankly speaking, I'm not sure this function is useful or correct at all -- > with the DMA timings being actually programmed in sl82c105_bmdma_start()... It ought to be right - bmdma_start loads the real DMA mode - set_dmamode/set_piomode load the right PIO timings - bmdma_stop restores the right PIO timings > And the issue of the same registers being used for both PIO and DMA timings is > not specific for this driver at all but seems to be addressed only by it... For most drivers (those using the ata_timing interface) the timing merge is done by ata_timing_compute(). > Signed-off-by: Sergei Shtylyov <sshtylyov@xxxxxxxxxxxxx> Acked-by: Alan Cox <alan@xxxxxxxxxx> - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
