On 1/30/07, Steven Scholz <steven.scholz@xxxxxxxxxxxxx> wrote:
I have connected HDD's A[2..0] to CPU's A[3..1] and do something like
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw.io_ports[i] = ide_virt_base + (i << 1);
}
thus all HDD registers are accessed on a 16bit aligned address. Thus
ide_inb() should return the correct value.
And btw are things like identify driver use 8bit transfers?
How could one then explain
current capacity is 78140160 sectors would be 0x000004A85300
native capacity is 185074430006016 sectors would be 0xA852FFA85300
? First three bytes ok, then the other three bytes rubbish?
Steven
Maybe I am misunderstanding the issue, but the upper 3 bytes (and in
fact all the extended registers) of a 48-bit LBA address are found by
re-reading the taskfile registers after setting the HOB bit (bit 7) in
the device control register. If your FPGA is simulating a taskfile
for the generic driver to read, then your FPGA will need to perform
this access on the device to simulate the extended taskfile registers.
In the above log, your upper 3 bytes appear to be garbage.
This is documented in the description of the "48-bit Address Feature
Set" in recent ATA specifications. Recent working draft
specifications are available from www.t13.org for anyone to browse and
download.
--eric
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