Alan wrote:
>> Hmm. Don't think so. Since the use of ioremap() I think the MMU treats the
>> area as none-cacheable, right?
>
> Thats only the first half of the story. If you don't decode byte level
> fetches in the FPGA or the code is doing something like
>
>
> read 16 bit value
> shift 8
> return half
>
> for 8 bit reads you'll get wrong answers.
I have connected HDD's A[2..0] to CPU's A[3..1] and do something like
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw.io_ports[i] = ide_virt_base + (i << 1);
}
thus all HDD registers are accessed on a 16bit aligned address. Thus
ide_inb() should return the correct value.
And btw are things like identify driver use 8bit transfers?
How could one then explain
current capacity is 78140160 sectors would be 0x000004A85300
native capacity is 185074430006016 sectors would be 0xA852FFA85300
? First three bytes ok, then the other three bytes rubbish?
Steven
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