On Tue, 28 Nov 2006, Jeff Garzik wrote: > > I was sorta wondering in that direction too. If its in legacy mode (PATA and > SATA smushed together), that's a possibility. But native or AHCI modes, the > channels are pretty independent (which is the nature of SATA). Well, what I was more wondering about is whether perhaps the legacy mode emulation - even when it isn't actually used - means that there is simply some shared state (read: chipset bug that nobody noticed). > Historical note: ata_piix is IMO more complicated than ahci, because the > silicon is emulating the PATA interface using an internal (probably huge) > state machine, converting PATA behavior to sending/receiving SATA packets. Well, there's bound to be the same big state machine working the other way, and maybe the chip simply internally gets confused. Or, as you say, simply because the emulation state machinery has to be taken into account, and _that_ ends up beign shared between the two otherwise independent channels.. How hard would it be to just force a shared spinlock between two sata channels on the same "controller"? It sounds like Jonas has a very repeatable setup, so even if I can't repeat my problem, if the performance degradation on writes is related, he can check his thing.. Linus - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
