On 8/31/06, Mark Lord <liml@xxxxxx> wrote:
Mark Odell wrote: > For PIO mode transfers, you should not have cache coherency issues since > the CPU core is doing the read from/write to hardware. One might think so, but cache lines are tagged with virtual addresses, so using different virtual addresses (kernel vs. userspace) for the same data can result in problems like this. There was a recent thread (this past winter, I believe) devoted to trying to resolve this issue in 2.6.xx, but I don't remember the final outcome.
http://marc.theaimsgroup.com/?l=linux-arm-kernel&m=107384066503818&w=2 http://marc.theaimsgroup.com/?l=linux-arm-kernel&m=107391014528541&w=2 http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-May/022262.html http://marc.theaimsgroup.com/?l=linux-ide&m=113517364630085&w=2 http://lkml.org/lkml/2006/1/13/156 and its associated posts There are probably others. I think Tejun would know best the status of this issue. Matt - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
