Mark Odell wrote:
For PIO mode transfers, you should not have cache coherency issues since
the CPU core is doing the read from/write to hardware.
One might think so, but cache lines are tagged with virtual addresses,
so using different virtual addresses (kernel vs. userspace) for the
same data can result in problems like this.
There was a recent thread (this past winter, I believe) devoted to
trying to resolve this issue in 2.6.xx, but I don't remember the final outcome.
Cheers
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