Hi, We use sg/libata for data read/write test in ARM XScale platform (VIVT cache). We experienced data miscompare issue during heavy testing on both DMA and PIO read/write. In this particular application, data buffer is allocated inside sg using alloc_pages() and mmapped to user space. So essentially this buffer can be accessed by user space, kernel for PIO and hardware for DMA. After changing mmapped vma to noncache, we haven't seen any data miscompare in DMA read/write, but data miscompare in PIO read/write still exists sporadically. I suspect this is caused by kernel cache alias during PIO read/write. What I want to know is how the cache coherency is ensured in PIO read/write. As an alternative, is there any way to make the kernel access to this data buffer uncached? Thanks, Fajun - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
