Jim Hull wrote:
Not just crazy, but wrong - this *can* happen on pre-Montecito. Even though L1D is write-through and L2 was mixed I/D, the L1 I-cache could contain stale instrutions if there are missing flushes.
I cannot agree with you. In order to consider an L1 I-cache entry as valid, a corresponding virtual -> physic address translation should be valid in one of the L1 ITLBs. "See 6.1.1. Instruction TLBS" of the I2 Proc. Ref. Man. for SW Dev. & Opt. You cannot have a valid L1 ITLB entry unless you have a corresponding valid L2 ITLB entry. When you remove a PTE (or switch off the exec bit) and you flush the L2 ITLB matching the old translation (and you kill the corresponding L1 ITLBs), you do invalidate the corresponding L1 I-cache entries. Therefore CPU models without split L2 caches are safe. Thanks, Zoltan - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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