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Hi i2c list maintainers,
This patch adjusted the LOW period of the SCL clock for a more accurate
i2c bus speed frequency. The given LOW period of the SCL clock 4.7us
would result an i2c bus speed of 105kHz (observed by oscilloscope).
Using 5.2us will have i2c bus speed frequency of 100kHz that match the
setting of I2C_MAX_STANDARD_MODE_FREQ 100 kHz.
BruceL |
From a83ed73f0a17eefea6a39d4723b6247612550ad1 Mon Sep 17 00:00:00 2001 From: Bruce Li <Bruce.Li@xxxxxxxxxxxxxxxxxxx> Date: Fri, 12 Jul 2024 14:12:14 +1200 Subject: [PATCH] i2c: designware: Adjust LOW period of the SCL clock This patch adjusted the LOW period of the SCL clock for a more accurate i2c bus speed frequency. The given LOW period of the SCL clock 4.7us would result an i2c bus speed of 105kHz (observed by oscilloscope). Using 5.2us will have i2c bus speed frequency of 100kHz that match the setting of I2C_MAX_STANDARD_MODE_FREQ 100 kHz. Signed-off-by: Bruce Li <Bruce.Li@xxxxxxxxxxxxxxxxxxx> --- drivers/i2c/busses/i2c-designware-master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c index c7e56002809a..ec731390947c 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -71,7 +71,7 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 0); /* No offset */ dev->ss_lcnt = i2c_dw_scl_lcnt(ic_clk, - 4700, /* tLOW = 4.7 us */ + 5200, /* tLOW = 5.2 us */ scl_falling_time, 0); /* No offset */ } -- 2.45.2
