Re: [PATCH] i2c: designware: Adjust LOW period of the SCL clock

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Hi Bruce,

On Fri, Jul 12, 2024 at 02:25:17AM GMT, Bruce Li wrote:
> Hi i2c list maintainers, 
> 
> This patch adjusted the LOW period of the SCL clock for a more accurate
> i2c bus speed frequency. The given LOW period of the SCL clock 4.7us
> would result an i2c bus speed of 105kHz (observed by oscilloscope).
> Using 5.2us will have i2c bus speed frequency of 100kHz that match the
> setting of I2C_MAX_STANDARD_MODE_FREQ 100 kHz.

Thanks for your patch but the way you sent it is not totally
right and this is the main reason no one has looked into it.

Please, after having done "git-commit" and "git-format-patch",
please use "git-send-email" and add in Cc the right people by
using

./scripts/get_maintainer.pl 0001-i2c-designware-Adjust-LOW-period-of-the-SCL-clock.patch

Andi




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