On Tue, Jan 9, 2024 at 7:00 AM Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> wrote:
>
> Remove the reg-io-width property in order to comply with the bindings.
>
> The entire bus (PERIC) on which the GS101 serial resides only allows
> 32-bit register accesses. The reg-io-width dt property is disallowed
> for the "google,gs101-uart" compatible and instead the iotype is
> inferred from the compatible.
>
> Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx>
> ---
Reviewed-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
Just out of curiosity (I probably missed the relevant discussion
earlier): what is the actual reason for moving 'reg-io-width' to the
driver's code as 'iotype'? I mean, what is the actual problem that's
being solved by this -- is it to make the earlycon functional for
gs101? I'm asking because the bus width looks like a part of HW
description, which usually belongs to dts, from the design point of
view. Anyways, that's not a concern, just trying to understand the
decision.
> v3: collect Peter's R-b tag
> v2: new patch
>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index d838e3a7af6e..4e5f4c748906 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -366,7 +366,6 @@ usi_uart: usi@10a000c0 {
> serial_0: serial@10a00000 {
> compatible = "google,gs101-uart";
> reg = <0x10a00000 0xc0>;
> - reg-io-width = <4>;
> interrupts = <GIC_SPI 634
> IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> --
> 2.43.0.472.g3155946c3a-goog
>
>
