On 1/16/24 17:57, Sam Protsenko wrote: > On Tue, Jan 9, 2024 at 7:00 AM Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> wrote: >> Remove the reg-io-width property in order to comply with the bindings. >> >> The entire bus (PERIC) on which the GS101 serial resides only allows >> 32-bit register accesses. The reg-io-width dt property is disallowed >> for the "google,gs101-uart" compatible and instead the iotype is >> inferred from the compatible. >> >> Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> >> --- > Reviewed-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx> > > Just out of curiosity (I probably missed the relevant discussion > earlier): what is the actual reason for moving 'reg-io-width' to the > driver's code as 'iotype'? I mean, what is the actual problem that's The majority (if not all?) of the hardware blocks in GS101 SoC require 32 bit register access widths. Instead of specifying reg-io-width = 4 everywhere in the device tree, we infer it from the compatibles. The relevant discussion is here: https://lore.kernel.org/linux-arm-kernel/db368449-f446-47e8-81b6-a11c2a872306@xxxxxxxxxx/ Cheers, ta > being solved by this -- is it to make the earlycon functional for > gs101? I'm asking because the bus width looks like a part of HW > description, which usually belongs to dts, from the design point of > view. Anyways, that's not a concern, just trying to understand the > decision.
