This driver uses cd6h/cd7h port I/O to access the FCH::PM::DECODEEN and FCH::PM::ISACONTROL registers during driver initialization. cd6h/cd7h port I/O is no longer supported on later AMD processors and the recommended method to access these registers is using MMIO. This series will replace the cd6h/cd7h port I/O with MMIO accesses during initialization. The first patch refactors watchdog timer initialization into a separate function. This is needed to add support for new device layouts without adding complexity. The second patch moves region request/release into new functions. The request/release functions provide a location for adding MMIO region support. The third patch introduces EFCH initialization using MMIO. This is required because the registers are no longer accessible using cd6h/cd7h port I/O. The fourth patch adds SMBus controller PCI ID check to enable EFCH MMIO initialization. This eliminates the need for driver updates to support future processors supporting the same EFCH functionality. Important: This series includes patches with MMIO accesses to registers FCH::PM::DECODEEN and FCH::PM::ISACONTROL. The same registers are also accessed by the piix4_smbus driver. The registers are currently accessed indirectly through cd6h/cd7h port I/O and both drivers use request_muxed_region() to synchronize the accesses. It should be noted the request_muxed_region() uses a wait queue to sleep and retry taking exclusive access if the port I/O region is busy. This series uses request_mem_region() to synchronize accesses to the MMIO registers mentioned above. request_mem_region() is missing the retry logic in the case the resource is busy. As a result, request_mem_region() will fail immediately if the resource is busy. The 'muxed' variant is needed here but request_muxed_mem_region() is not defined to use. I will follow up with another patch series to define the request_muxed_mem_region() and use in both drivers. The piix4_smbus driver or the sp5100_tco driver can potentialy fail until the muxed mem synchronization series is present in the tree. The potential for failure is not likely because the sp5100_tco driver only accesses the FCH::PM::DECODEEN and FCH::PM::ISACONTROL registers during driver initialization. Link: https://lore.kernel.org/all/20210715221828.244536-1-Terry.Bowman@xxxxxxx/#t Based on v5.16 Testing: Tested on AMD family 17h and family 19h processors using: cat >> /dev/watchdog Changes in V3: - Remove 'addr' and 'res' variables from struct sp5100_tco. (Guenter Roeck) - Pass address directly to efch_read_pm_reg8() and efch_update_pm_reg8(). (Guenter Roeck) - Reword patch descriptions. (Terry Bowman) - Change #define AMD_ZEN_SMBUS_PCI_REV value from 0x59 to 0x51. This was determined after investigating programmers manual and testing. (Robert Richter) - Refactor efch_* functions() (Robert Richter) - Remove trailing whitespace in patch. (Guenter Roeck) Terry Bowman (4): Watchdog: sp5100_tco: Move timer initialization into function Watchdog: sp5100_tco: Refactor MMIO base address initialization Watchdog: sp5100_tco: Add initialization using EFCH MMIO Watchdog: sp5100_tco: Enable Family 17h+ CPUs drivers/watchdog/sp5100_tco.c | 335 ++++++++++++++++++++++------------ drivers/watchdog/sp5100_tco.h | 6 + 2 files changed, 227 insertions(+), 114 deletions(-) -- 2.30.2
