On Fri, Aug 14, 2020 at 09:02:59PM +0200, Andrew Lunn wrote: > On Fri, Aug 14, 2020 at 02:56:58PM -0400, Mohammed Billoo wrote: > > Sadly, this is a case of vendor-specific implementations causing indigestion. > > When this was implemented on the FPGA, the vendor-specific AHB bridge (we're > > going from PCI to AHB to grlib) had a built-in endianness conversion which we > > didn't want and found out later. Since it was easier to add the big endian > > accessor on the software side instead of redoing the FPGA design, we opted for > > the former. > > O.K. So please document this is a workaround for broken hardware. > Otherwise other people are going to ask the same question. Add it to > the commit message at least. Very true, this should be documented. I think a comment in the source code makes more sense.
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