On Fri, Aug 14, 2020 at 12:31:34PM -0400, Mohammed Billoo wrote:
> Add be/le accessors for grlib (as is done for the standard ocore
> accessors).
I thought PCI standardised the endianness of the bus? So long as you
use the right wrappers, it should not matter what the endianness of
the CPU is.
Andrew
