Add be/le accessors for grlib (as is done for the standard ocore
accessors).
Signed-off-by: Mohammed Billoo <mab@xxxxxxxxxxxx>
---
arch/arm/configs/socfpga_defconfig | 1 +
drivers/i2c/busses/i2c-ocores.c | 55 ++++++++++++++++++++++++++----
2 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index e73c97b0f5b0..55bf9cfcf75c 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -162,3 +162,4 @@ CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_FUNCTION_TRACER=y
CONFIG_DEBUG_USER=y
+CONFIG_I2C_OCORES=y
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 0975f6797069..a5f9e6cb4814 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -492,7 +492,7 @@ MODULE_DEVICE_TABLE(of, ocores_i2c_match);
* 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
* register. The subsequent registers have their offsets decreased accordingly.
*/
-static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
+static u8 oc_getreg_grlib_be(struct ocores_i2c *i2c, int reg)
{
u32 rd;
int rreg = reg;
@@ -506,7 +506,7 @@ static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
return (u8)rd;
}
-static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
+static void oc_setreg_grlib_be(struct ocores_i2c *i2c, int reg, u8 value)
{
u32 curr, wr;
int rreg = reg;
@@ -525,6 +525,39 @@ static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
}
+static u8 oc_getreg_grlib_le(struct ocores_i2c *i2c, int reg)
+{
+ u32 rd;
+ int rreg = reg;
+
+ if (reg != OCI2C_PRELOW)
+ rreg--;
+ rd = ioread32(i2c->base + (rreg << i2c->reg_shift));
+ if (reg == OCI2C_PREHIGH)
+ return (u8)(rd >> 8);
+ else
+ return (u8)rd;
+}
+
+static void oc_setreg_grlib_le(struct ocores_i2c *i2c, int reg, u8 value)
+{
+ u32 curr, wr;
+ int rreg = reg;
+
+ if (reg != OCI2C_PRELOW)
+ rreg--;
+ if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
+ curr = ioread32(i2c->base + (rreg << i2c->reg_shift));
+ if (reg == OCI2C_PRELOW)
+ wr = (curr & 0xff00) | value;
+ else
+ wr = (((u32)value) << 8) | (curr & 0xff);
+ } else {
+ wr = value;
+ }
+ iowrite32(wr, i2c->base + (rreg << i2c->reg_shift));
+}
+
static int ocores_i2c_of_probe(struct platform_device *pdev,
struct ocores_i2c *i2c)
{
@@ -592,8 +625,13 @@ static int ocores_i2c_of_probe(struct platform_device *pdev,
match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
if (match && (long)match->data == TYPE_GRLIB) {
dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
- i2c->setreg = oc_setreg_grlib;
- i2c->getreg = oc_getreg_grlib;
+ if (of_device_is_big_endian(pdev->dev.of_node)) {
+ i2c->setreg = oc_setreg_grlib_be;
+ i2c->getreg = oc_getreg_grlib_be;
+ } else {
+ i2c->setreg = oc_setreg_grlib_le;
+ i2c->getreg = oc_getreg_grlib_le;
+ }
}
return 0;
@@ -648,8 +686,13 @@ static int ocores_i2c_probe(struct platform_device *pdev)
else
i2c->bus_clock_khz = 100;
if (pdata->gaisler) {
- i2c->setreg = oc_setreg_grlib;
- i2c->getreg = oc_getreg_grlib;
+ if (pdata->big_endian) {
+ i2c->setreg = oc_setreg_grlib_be;
+ i2c->getreg = oc_getreg_grlib_be;
+ } else {
+ i2c->setreg = oc_setreg_grlib_le;
+ i2c->getreg = oc_getreg_grlib_le;
+ }
}
} else {
ret = ocores_i2c_of_probe(pdev, i2c);
--
2.17.1
