Re: i2c-designware regression

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Hi

On 09/30/2018 08:30 PM, Ard Biesheuvel wrote:
Hello all,

With v4.19-rc6, I am seeing the splat below, which I *think* may be caused by

commit 3bd4f277274bd7dde65879e5c8cd16d0b34eba90
Author: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx>
Date:   Tue Jun 19 14:23:21 2018 +0300

     i2c: designware: Call i2c_dw_clk_rate() only once in i2c_dw_init_master()

     This is rather readability update than micro-optimization, or if not
     optimization at all. We take the input clock rate to a variable and pass
     that to SCL timing parameter calculation functions.

     Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
     Signed-off-by: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx>
     Signed-off-by: Wolfram Sang <wsa@xxxxxxxxxxxxx>

Note that this is an arm64 ACPI system.

Cheers,
Ard.



WARNING: CPU: 3 PID: 1 at
/home/ard/linux-2.6/drivers/i2c/busses/i2c-designware-common.c:245
i2c_dw_clk_rate+0x38/0x50

Thanks, it was the blast from the past I forgot: b33af11de236 ("i2c: designware: Do not require clock when SSCN and FFCN are provided"). I'll cook a patch.

--
Jarkko



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