On Thu, Aug 23, 2018 at 03:57:31PM -0700, Jae Hyun Yoo wrote: > In most of cases, interrupt bits are set one by one but there are > also a lot of other cases that Aspeed I2C IP sends multiple > interrupt bits with combining master and slave events using a > single interrupt call. It happens much more in multi-master > environment than single-master. For an example, when master is > waiting for a NORMAL_STOP interrupt in its MASTER_STOP state, > SLAVE_MATCH and RX_DONE interrupts could come along with the > NORMAL_STOP in case of an another master immediately sends data > just after acquiring the bus. In this case, the NORMAL_STOP > interrupt should be handled by master_irq and the SLAVE_MATCH and > RX_DONE interrupts should be handled by slave_irq. This commit > modifies irq hadling logic to handle the master/slave combined > events properly. > > Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@xxxxxxxxxxxxxxx> Applied to for-next, thanks!
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