Re: [PATCH 1/1] i2c: cadance: (bugfix) ctrl/addr reg write order

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Wolfram,

On Thu, Jun 22, 2017 at 3:35 AM, Wolfram Sang <wsa@xxxxxxxxxxxxx> wrote:
> On Wed, Jun 21, 2017 at 08:45:26PM -0500, Matt Weber wrote:
>> The driver was clearing the hold bit in the control register before
>> writing to the address register which resulted in a stop condition
>> being generated rather than a repeated start.
>>
>> This issue was only observed when a system was running much
>> slower than a normal processor would execute.  The IP data sheet
>> mentions a ordering of writing to the address register before
>> clearing the hold.
>>
>> Signed-off-by: John Linn <john.linn@xxxxxxxxxx>
>> Signed-off-by: Paresh Chaudhary <paresh.chaudhary@xxxxxxxxxxxxxxxxxxx>
>> Signed-off-by: Matthew Weber <matthew.weber@xxxxxxxxxxxxxxxxxxx>
>
> Looks good. It seems not urgent to me, though. Are you fine with me
> scheduling it for 4.13 yet with a stable tag attached? Or do you
> consider it 4.12 material? And if you could provide a Fixes: tag that
> would be helpful.
>

Not urgent, fell free to work it in where it makes sense. We're on a
older LTS at this point and will carry the patch.

For the Fixes: tag in this case, should I just prefix my last
statement about the issue as there isn't a public bug report or
specific commit I can note?  I could add cadence ref manual section
and a link to a public download of the doc.

Matt



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