Re: [PATCH 1/1] i2c: cadance: (bugfix) ctrl/addr reg write order

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On Wed, Jun 21, 2017 at 08:45:26PM -0500, Matt Weber wrote:
> The driver was clearing the hold bit in the control register before
> writing to the address register which resulted in a stop condition
> being generated rather than a repeated start.
> 
> This issue was only observed when a system was running much
> slower than a normal processor would execute.  The IP data sheet
> mentions a ordering of writing to the address register before
> clearing the hold.
> 
> Signed-off-by: John Linn <john.linn@xxxxxxxxxx>
> Signed-off-by: Paresh Chaudhary <paresh.chaudhary@xxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Matthew Weber <matthew.weber@xxxxxxxxxxxxxxxxxxx>

Looks good. It seems not urgent to me, though. Are you fine with me
scheduling it for 4.13 yet with a stable tag attached? Or do you
consider it 4.12 material? And if you could provide a Fixes: tag that
would be helpful.

Thanks for the patch!

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