> Is there such implementation (couldn't find any in the list history)? Nope. > Are there any restrictions to implement one? Honestly, I don't think this is feasible. Even at a kind of slow bus speed of 100 kHz, you'd probably create quite some load. And since you don't have any guarantee of interrupt latency being below your desired threshold, you have no guarantee to keep up with the timing of the master. Which you must.
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