Re: [PATCH v1 4/4] pinctrl: intel: Convert capability list to features

[Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>]

On Fri, Jan 08, 2021 at 02:51:09PM +0200, Andy Shevchenko wrote:
> On Fri, Jan 8, 2021 at 2:46 PM Mika Westerberg
> <mika.westerberg@xxxxxxxxxxxxxxx> wrote:
> > On Fri, Jan 08, 2021 at 02:31:23PM +0200, Andy Shevchenko wrote:
> > > On Fri, Jan 8, 2021 at 2:22 PM Andy Shevchenko
> > > <andy.shevchenko@xxxxxxxxx> wrote:
> > > > On Fri, Jan 8, 2021 at 9:09 AM Mika Westerberg
> > > > <mika.westerberg@xxxxxxxxxxxxxxx> wrote:
> 
> ...
> 
> > > > I don't see how it could be achieved (offsets can be unordered). If
> > > > there is such an issue it will mean a silicon bug.
> > >
> > > Specification says clearly that one register is a must and its value
> > > defines the behaviour.
> > >
> > > "The first Capability List register is located at offset 0x004...  and
> > > contains a pointer/address to the next Capability List register. The
> > > first Capability List register is no different than others... except
> > > for its “Capability Identification” field is always 0. The total
> > > number of Capability List registers... is 1 at the minimum (to
> > > determine if there is any capability)."
> >
> > This is not the first time something like this is done wrong at silicon
> > level.
> 
> I agree. What about solving the issue when it comes?

Up to you :)

> > IMHO it is always good idea to avoid possible infinite loops
> > especially in the kernel space.
> 
> But do PCI / xHCI (the first two that came to my mind) have something like this?

Yes they do, at least PCI. I would expect xHCI to have it too as the
hardware can be hot removed in the middle of a capability list walk
returning 1's on subsequent reads.