On Fri, Jan 8, 2021 at 2:22 PM Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote: > On Fri, Jan 8, 2021 at 9:09 AM Mika Westerberg > <mika.westerberg@xxxxxxxxxxxxxxx> wrote: > > On Thu, Jan 07, 2021 at 09:02:00PM +0200, Andy Shevchenko wrote: ... > I don't see how it could be achieved (offsets can be unordered). If > there is such an issue it will mean a silicon bug. Specification says clearly that one register is a must and its value defines the behaviour. "The first Capability List register is located at offset 0x004... and contains a pointer/address to the next Capability List register. The first Capability List register is no different than others... except for its “Capability Identification” field is always 0. The total number of Capability List registers... is 1 at the minimum (to determine if there is any capability)." So I prefer to stick with my original variant. -- With Best Regards, Andy Shevchenko