Re: EFI: Stash ROMs if they're not in the PCI BAR

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On Fri, 2013-03-15 at 08:57 +0000, David Woodhouse wrote:
> On Fri, 2013-03-15 at 11:29 +0300, Dan Carpenter wrote:
> > Hello Matthew Garrett,
> > 
> > The patch dd5fc854de5f: "EFI: Stash ROMs if they're not in the PCI 
> > BAR" from Dec 5, 2012, leads to the following warning:
> > "arch/x86/boot/compressed/eboot.c:290 setup_efi_pci()
> > 	 error: potentially dereferencing uninitialized 'pci_handle'."
> > 
> >   254  static efi_status_t setup_efi_pci(struct boot_params *params)
> >   255  {
> >   256          efi_pci_io_protocol *pci;
> >   257          efi_status_t status;
> >   258          void **pci_handle;
> >   259          efi_guid_t pci_proto = EFI_PCI_IO_PROTOCOL_GUID;
> >   260          unsigned long nr_pci, size = 0;
> >   261          int i;
> >   262          struct setup_data *data;
> >   263  
> >   264          data = (struct setup_data *)(unsigned long)params->hdr.setup_data;
> >   265  
> >   266          while (data && data->next)
> >   267                  data = (struct setup_data *)(unsigned long)data->next;
> >   268  
> >   269          status = efi_call_phys5(sys_table->boottime->locate_handle,
> >   270                                  EFI_LOCATE_BY_PROTOCOL, &pci_proto,
> >   271                                  NULL, &size, pci_handle);
> >                                                     ^^^^^^^^^^
> > This hasn't been initialized yet.
> 
> True. It probably doesn't *matter* because the size is zero so the
> firmware is just going to ignore the pointer anyway. Although in that
> case I wonder why we couldn't have just passed NULL. Perhaps we expected
> that some firmware might do some validation on the pointer before
> getting to the size check?

I doubt that the firmware checks the validity of pci_handle when size is
zero, and I agree it's worth passing NULL to silence the warning (which
is also more explicit that just initialising pci_handle), unless Matthew
knows of a reason we shouldn't do that?

-- 
Matt Fleming, Intel Open Source Technology Center

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