From: Sebastian Lawniczak <sebastian.lawniczak@xxxxxxxxx>
Fix warnings reported by checkpatch.pl in block comments.
Signed-off-by: Sebastian Lawniczak <sebastian.lawniczak@xxxxxxxxx>
---
drivers/staging/sm750fb/ddk750_chip.c | 70 +++++++++++++++++++----------------
1 file changed, 39 insertions(+), 31 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c
index 0331d34..01ddf44 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -86,8 +86,10 @@ static void setMemoryClock(unsigned int frequency)
return;
if (frequency) {
- /* Set the frequency to the maximum frequency that the DDR Memory can take
- which is 336MHz. */
+ /*
+ * Set the frequency to the maximum frequency that the DDR Memory can take
+ * which is 336MHz.
+ */
if (frequency > MHz(336))
frequency = MHz(336);
@@ -133,8 +135,10 @@ static void setMasterClock(unsigned int frequency)
return;
if (frequency) {
- /* Set the frequency to the maximum frequency that the SM750 engine can
- run, which is about 190 MHz. */
+ /*
+ * Set the frequency to the maximum frequency that the SM750 engine can
+ * run, which is about 190 MHz.
+ */
if (frequency > MHz(190))
frequency = MHz(190);
@@ -168,11 +172,11 @@ unsigned int ddk750_getVMSize(void)
unsigned int reg;
unsigned int data;
- /* sm750le only use 64 mb memory*/
+ /* sm750le only use 64 mb memory */
if (getChipType() == SM750LE)
return SZ_64M;
- /* for 750,always use power mode0*/
+ /* for 750,always use power mode0 */
reg = PEEK32(MODE0_GATE);
reg = FIELD_SET(reg, MODE0_GATE, GPIO, ON);
POKE32(MODE0_GATE, reg);
@@ -203,7 +207,7 @@ int ddk750_initHw(initchip_param_t *pInitParam)
pInitParam->powerMode = 0;
setPowerMode(pInitParam->powerMode);
- /* Enable display power gate & LOCALMEM power gate*/
+ /* Enable display power gate & LOCALMEM power gate */
ulReg = PEEK32(CURRENT_GATE);
ulReg = FIELD_SET(ulReg, CURRENT_GATE, DISPLAY, ON);
ulReg = FIELD_SET(ulReg, CURRENT_GATE, LOCALMEM, ON);
@@ -233,10 +237,11 @@ int ddk750_initHw(initchip_param_t *pInitParam)
setMasterClock(MHz(pInitParam->masterClock));
- /* Reset the memory controller. If the memory controller is not reset in SM750,
- the system might hang when sw accesses the memory.
- The memory should be resetted after changing the MXCLK.
- */
+ /*
+ * Reset the memory controller. If the memory controller is not reset in SM750,
+ * the system might hang when sw accesses the memory.
+ * The memory should be resetted after changing the MXCLK.
+ */
if (pInitParam->resetMemory == 1) {
ulReg = PEEK32(MISC_CTRL);
ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, RESET);
@@ -279,20 +284,20 @@ int ddk750_initHw(initchip_param_t *pInitParam)
}
/*
- monk liu @ 4/6/2011:
- re-write the calculatePLL function of ddk750.
- the original version function does not use some mathematics tricks and shortcut
- when it doing the calculation of the best N,M,D combination
- I think this version gives a little upgrade in speed
-
- 750 pll clock formular:
- Request Clock = (Input Clock * M )/(N * X)
-
- Input Clock = 14318181 hz
- X = 2 power D
- D ={0,1,2,3,4,5,6}
- M = {1,...,255}
- N = {2,...,15}
+* monk liu @ 4/6/2011:
+* re-write the calculatePLL function of ddk750.
+* the original version function does not use some mathematics tricks and shortcut
+* when it doing the calculation of the best N,M,D combination
+* I think this version gives a little upgrade in speed
+*
+* 750 pll clock formular:
+* Request Clock = (Input Clock * M )/(N * X)
+*
+* Input Clock = 14318181 hz
+* X = 2 power D
+* D ={0,1,2,3,4,5,6}
+* M = {1,...,255}
+* N = {2,...,15}
*/
unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll)
{
@@ -306,8 +311,10 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll)
int max_d;
if (getChipType() == SM750LE) {
- /* SM750LE don't have prgrammable PLL and M/N values to work on.
- Just return the requested clock. */
+ /*
+ * SM750LE don't have prgrammable PLL and M/N values to work on.
+ * Just return the requested clock.
+ */
return request_orig;
}
@@ -358,10 +365,11 @@ unsigned int formatPllReg(pll_value_t *pPLL)
{
unsigned int ulPllReg = 0;
- /* Note that all PLL's have the same format. Here, we just use Panel PLL parameter
- to work out the bit fields in the register.
- On returning a 32 bit number, the value can be applied to any PLL in the calling function.
- */
+ /*
+ * Note that all PLL's have the same format. Here, we just use Panel PLL parameter
+ * to work out the bit fields in the register.
+ * On returning a 32 bit number, the value can be applied to any PLL in the calling function.
+ */
ulPllReg =
FIELD_SET(0, PANEL_PLL_CTRL, BYPASS, OFF)
| FIELD_SET(0, PANEL_PLL_CTRL, POWER, ON)
--
2.6.2
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