This is a request for comments on high level design of Tegra config settings. NVIDIA Tegra SoCs have various I/O controllers and these controllers require specific register configurations based on: - Functional mode (eg. speed) - Interface properties (eg. signal timings) - Manufacturing characteristics (eg. process/package) - Thermal characteristics - Board characteristics Some of the configurations can be provided by device specific standard DT properties like speed of interface in I2C, rising/falling timing etc. However, there are more device specific configurations required to tune the interface based on execution mode or other runtime parameters. All such configurations are defined as 'config' settings of the device. This configures a device to operate with the optimal settings for a particular mode to improve performance, stability or reduce power. Add the mechanism to provide the configuration parameters from the device tree called "config setting via Device Tree". This series capture the device tree details, common parser code for Tegra SOC and the usage in I/O controllers I2C, SPI. Patch 01: Documentation about the device tree binding for common config framework. Patch 02: Device tree binding documentation for config setting. Patch 03: Common parser of the device tree config setting node for Tegra SoC. Patch 04: Device tree binding documentation for the I2C config setting. Patch 05: Add phandle reference for the I2C config setting. Patch 06: Move clock initialization code into new methods Patch 07: Using config settings in Tegra I2C driver for interface timing registers. Patch 08: Add Tegra234 I2C config settings in DT. Patch 09: Device tree binding documentation for the SDHCI config setting. Patch 10: Add phandle reference for the SDHCI config setting. Patch 11: Using config settings in Tegra SDHCI driver for tuning iteration. Patch 12: Add Tegra234 SDHCI config settings in DT. Changes in V2: - Move config settings to a new node - Use phandles to refer config settings in device node - Update subject of dt patches Open to review: - All config settings are field (bits) entries and input in hex format. This would allow parsing and updating registers easier. Krishna Yarlagadda (12): Documentation: Introduce config settings framework dt-bindings: misc: Tegra configuration settings soc: tegra: Add config setting framework dt-bindings: misc: tegra-i2c: config settings dt-bindings: i2c: tegra-i2c: reference to config i2c: tegra: split clock initialization code i2c: tegra: config settings for interface timings arm64: tegra: I2C interface timings dt-bindings: misc: tegra-sdhci: config settings dt-bindings: mmc: tegra-sdhci: reference to config mmc: host: tegra: config settings for timing arm64: tegra: SDHCI timing settings .../bindings/i2c/nvidia,tegra20-i2c.yaml | 5 + .../misc/nvidia,tegra-config-settings.yaml | 158 ++++++ .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 4 + Documentation/misc-devices/tegra-cfg.rst | 133 +++++ MAINTAINERS | 10 + arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi | 501 ++++++++++++++++++ .../dts/nvidia/tegra234-p3701-0000-cfg.dtsi | 107 ++++ .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 1 + drivers/i2c/busses/i2c-tegra.c | 257 +++++++-- drivers/mmc/host/sdhci-tegra.c | 84 +++ drivers/soc/tegra/Makefile | 1 + drivers/soc/tegra/tegra-cfg.c | 147 +++++ include/soc/tegra/tegra-cfg.h | 87 +++ 13 files changed, 1442 insertions(+), 53 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra-config-settings.yaml create mode 100644 Documentation/misc-devices/tegra-cfg.rst create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3701-0000-cfg.dtsi create mode 100644 drivers/soc/tegra/tegra-cfg.c create mode 100644 include/soc/tegra/tegra-cfg.h -- 2.43.2
