Hi Charlie, On 2024-06-19 6:57 PM, Charlie Jenkins wrote: > The D1/D1s SoCs support xtheadvector so it can be included in the > devicetree. Also include vlenb for the cpu. > > Signed-off-by: Charlie Jenkins <charlie@xxxxxxxxxxxx> > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- The other C906/C910/C920-based SoCs need devicetree updates as well, although they don't necessarily need to be part of this series: - sophgo/cv18xx.dtsi - sophgo/sg2042-cpus.dtsi - thead/th1520.dtsi > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 64c3c2e6cbe0..6367112e614a 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > riscv,isa = "rv64imafdc"; The ISA string should be updated to keep it in sync with riscv,isa-extensions. Regards, Samuel > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > + "zifencei", "zihpm", "xtheadvector"; > + thead,vlenb = <128>; > #cooling-cells = <2>; > > cpu0_intc: interrupt-controller { >