> Hm.. good question. I didn't found the answer in the spec. By combining all > puzzle parts I assume, different Alternative configurations are designed > to handle conflict between "PSE Physical Layer classification" and PHY > autoneg. > > Here is how multi-pulse Physical Layer classification is done: > https://img.electronicdesign.com/files/base/ebm/electronicdesign/image/2020/07/Figure_5.5f2094553a61c.png > > this is the source: > https://www.electronicdesign.com/technologies/power/whitepaper/21137799/silicon-labs-90-w-power-over-ethernet-explained > > To avoid classification conflict with autoneg. Assuming, PHY on PD side > will be not powered until classification is completed. The only source > of pulses is the PHY on PSE side (if it is not under control of software > on PSE side or Midspan PSE is used), so aneg pulses should be send on > negative PoE pair? This all is just speculation, I would need to ask > some expert or do testing. > > If this assumption is correct, PHY framework will need to know exact > layout of MDI-X setting and/or silent PHY until PSE classification is done. Ideally, we don't want to define a DT binding, and then find it is wrong for 1000BaseT and above and we need to change it. So, either somebody needs to understand 1000BaseT and can say the proposed binding works, or we explicitly document the binding is limited to 10BaseT and 100BaseT. I'm not sure the second solution will actually fly. This was being tested with Marvell Prestera switch. I doubt it even has any Fast Ethernet ports. Andrew
