> With SNC enable, the L3 monitors are unaffected, but the controls behave as if they were > part of some other component in the system. I don't think of it like that. See attached picture of a single socket divided in two by SNC. [If the attachment is stripped off for those reading this via mailing lists, if you want the picture, just send me an e-mail.] Everything in blue is node 0. Yellow for node 1. The rectangles in the middle represent the L3 cache (12-way associative). When cores in node 0 access memory in node 0, it will be cached using the "top" half of the cache indices. Similarly for node 1 using the "bottom" half. Here’s how each of the Intel L3 resctrl functions operate with SNC enabled: CQM: Reports how much of your half of the L3 cache is occupied MBM: Reports on memory traffic from your half of the cache to your memory controllers. CAT: Still controls which ways of the cache are available for allocation (but each way has half the capacity.) MBA: The same throttling levels applied to "blue" and "yellow" traffic (because there are only socket level controls). > I'm a little nervous that the SNC support looks strange if we ever add support for > something like the above. Given its described in ACPI, I assume there are plenty of > machines out there that look like this. I'm also nervous as h/w designers find various ways to diverge from the old paradigm of socket scope == L3 cache scope == NUMA node scope -Tony
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SNC topology.png
Description: SNC topology.png
