On Mon, 20 Nov 2023 19:39:35 +0100 Andrew Lunn wrote: > > What about my use case of having a NIC which can stamp at a low rate > > at the PHY (for PTP) and high rate at the DMA block (for congestion > > control)? Both stamp points have the same PHC index. > > How theoretical is that? To me, it seems more likely you have two PHC. Very practical. mlx5 does this today, based on guessing and private ethtool flags. > The PHY stamping tends to be slow because of the MDIO bus. If the MAC > has fast access to the PHC, it means its not on the MDIO bus. It > probably means you have the PHY integrated into the MAC/SoC, so the > MAC can access it. But if its integrated like this, i don't see why > PHY stamping should be particularly slow. So you can probably use it > for congestion control. And then you don't need DMA stamping. Tx stamps are harder to carry back to the host all the way from the PHY than from the DMA block when DMA completion is signaled. Rx stamps seem much easier to carry down the pipeline but apparently some vendors are incapable of doing that as well. > Do you know of real hardware with a MAC and a PHY sharing a PHC? mlx5 for sure, but other designs, too. PHY, NIC pipeline and PCIe PTM may all need to time stamp from a single time counter.
