Hi Guo, On Sat, Jul 4, 2020 at 6:34 AM <guoren@xxxxxxxxxx> wrote: > > > There is no single step exception in riscv ISA, so utilize ebreak to > > > simulate. Some pc related instructions couldn't be executed out of line > > > and some system/fence instructions couldn't be a trace site at all. > > > So we give out a reject list and simulate list in decode-insn.c. On Sat, Jul 4, 2020 at 2:40 PM Pekka Enberg <penberg@xxxxxxxxx> wrote: > > Can you elaborate on what you mean by this? Why would you need a > > single-step facility for kprobes? Is it for executing the instruction > > that was replaced with a probe breakpoint? On Sat, Jul 4, 2020 at 5:55 PM Guo Ren <guoren@xxxxxxxxxx> wrote: > It's the single-step exception, not single-step facility! Aah, right, I didn't read the specification carefully enough. Thanks for taking the time to clarify this! FWIW, for the whole series: Reviewed-by: Pekka Enberg <penberg@xxxxxxxxxx> - Pekka
