On Sat, Jul 4, 2020 at 6:34 AM <guoren@xxxxxxxxxx> wrote: > The patchset includes kprobe/uprobe support and some related fixups. Nice! On Sat, Jul 4, 2020 at 6:34 AM <guoren@xxxxxxxxxx> wrote: > There is no single step exception in riscv ISA, so utilize ebreak to > simulate. Some pc related instructions couldn't be executed out of line > and some system/fence instructions couldn't be a trace site at all. > So we give out a reject list and simulate list in decode-insn.c. Can you elaborate on what you mean by this? Why would you need a single-step facility for kprobes? Is it for executing the instruction that was replaced with a probe breakpoint? Also, the "Debug Specification" [1] specifies a single-step facility for RISC-V -- why is that not useful for implementing kprobes? 1. https://riscv.org/specifications/debug-specification/ - Pekka
