Hi Pekka, On Sat, Jul 4, 2020 at 2:40 PM Pekka Enberg <penberg@xxxxxxxxx> wrote: > > On Sat, Jul 4, 2020 at 6:34 AM <guoren@xxxxxxxxxx> wrote: > > The patchset includes kprobe/uprobe support and some related fixups. > > Nice! > > On Sat, Jul 4, 2020 at 6:34 AM <guoren@xxxxxxxxxx> wrote: > > There is no single step exception in riscv ISA, so utilize ebreak to > > simulate. Some pc related instructions couldn't be executed out of line > > and some system/fence instructions couldn't be a trace site at all. > > So we give out a reject list and simulate list in decode-insn.c. > > Can you elaborate on what you mean by this? Why would you need a > single-step facility for kprobes? Is it for executing the instruction > that was replaced with a probe breakpoint? It's the single-step exception, not single-step facility! Other arches use hardware single-step exception for k/uprobe, eg: - powerpc: regs->msr |= MSR_SINGLESTEP - arm/arm64: PSTATE.D for enabling software step exceptions - s390: Set PER control regs, turns on single step for the given address - x86: regs->flags |= X86_EFLAGS_TF - csky: of course use hw single step :) Yes, All the above arches use a hardware single-step exception mechanism to execute the instruction that was replaced with a probe breakpoint. > > Also, the "Debug Specification" [1] specifies a single-step facility > for RISC-V -- why is that not useful for implementing kprobes? > > 1. https://riscv.org/specifications/debug-specification/ We need single-step exception not single-step by jtag, so above spec is not related to the patchset. See riscv-Privileged spec: Interrupt Exception Code-Description 1 0 Reserved 1 1 Supervisor software interrupt 1 2–4 Reserved 1 5 Supervisor timer interrupt 1 6–8 Reserved 1 9 Supervisor external interrupt 1 10–15 Reserved 1 ≥16 Available for platform use 0 0 Instruction address misaligned 0 1 Instruction access fault 0 2 Illegal instruction 0 3 Breakpoint 0 4 Load address misaligned 0 5 Load access fault 0 6 Store/AMO address misaligned 0 7 Store/AMO access fault 0 8 Environment call from U-mode 0 9 Environment call from S-mode 0 10–11 Reserved 0 12 Instruction page fault 0 13 Load page fault 0 14 Reserved 0 15 Store/AMO page fault 0 16–23 Reserved 0 24–31 Available for custom use 0 32–47 Reserved 0 48–63 Available for custom use 0 ≥64 Reserved No single step! So I insert a "ebreak" instruction behind the target single-step instruction to simulate the same mechanism. -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
