On Sat, 19 Aug 2023 at 06:12, Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx> wrote: > > On Fri, Aug 18, 2023 at 12:21:02PM +0200, Ard Biesheuvel wrote: > > > > IIRC there have been other cases (ThunderX?) where 128 bit MMIO > > accessors were needed for some peripheral, but common arm64 helpers > > were rejected on the basis that this atomic behavior is not > > architectural. > > > > Obviously, using inline asm in the driver is not the right way either, > > so perhaps we should consider introducing some common infrastructure > > anyway, including some expectation management about their guarantees. > > The ones in > > drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h > > look better. So perhaps copy them into hisilicon? > No, that otx2_write128() routine looks buggy, actually, The ! at the end means writeback, and so the register holding addr will be modified, which is not reflect in the asm constraints. It also lacks a barrier. The generic version just ORs the low and high qwords together, so it obviously only exists for compile coverage (and the generic atomic add is clearly broken too)
