On Fri, 18 Jun 2021 17:30:47 -0700 Jakub Kicinski wrote:
> On Thu, 17 Jun 2021 09:04:14 +0800 Yunsheng Lin wrote:
> > The spin_trylock() was assumed to contain the implicit
> > barrier needed to ensure the correct ordering between
> > STATE_MISSED setting/clearing and STATE_MISSED checking
> > in commit a90c57f2cedd ("net: sched: fix packet stuck
> > problem for lockless qdisc").
> >
> > But it turns out that spin_trylock() only has load-acquire
> > semantic, for strongly-ordered system(like x86), the compiler
> > barrier implicitly contained in spin_trylock() seems enough
> > to ensure the correct ordering. But for weakly-orderly system
> > (like arm64), the store-release semantic is needed to ensure
> > the correct ordering as clear_bit() and test_bit() is store
> > operation, see queued_spin_lock().
> >
> > So add the explicit barrier to ensure the correct ordering
> > for the above case.
> >
> > Fixes: a90c57f2cedd ("net: sched: fix packet stuck problem for lockless qdisc")
> > Signed-off-by: Yunsheng Lin <linyunsheng@xxxxxxxxxx>
>
> Acked-by: Jakub Kicinski <kuba@xxxxxxxxxx>
Actually.. do we really need the _before_atomic() barrier?
I'd think we only need to make sure we re-check the lock
after we set the bit, ordering of the first check doesn't
matter.
