On 9/28/20 4:27 AM, Joakim Zhang wrote:
>> If it's OK on all SoCs to initialize the complete RAM area, just do it. Then we can
>> get rid of the proposed struct at all.
>
> Should be OK according to IP guys feedbacks.
Good!
> static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
> .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
> FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
> FLEXCAN_QUIRK_BROKEN_PERR_STATE,
> };
>
> static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
> .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
> FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
> FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
> };
>
> static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
> .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
> FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
> FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD,
> };
> I am checking layerscape's CAN section:
>
> There is no ECC section in LS1021A
> https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-multicore-processors/layerscape-1021a-dual-core-communications-processor-with-lcd-controller:LS1021A?tab=Documentation_Tab
Hmmm, why does the LS1021A have "FLEXCAN_QUIRK_DISABLE_MECR"? The bits in the
ctrl2 and the mecr register itself used in the quirk are marked as reserved in
this datasheet....
Can @Pankaj Bansal clarify this?
> ECC section in LX2160A, also contains the same NOTE as i.MX8MP.
> https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-multicore-processors/layerscape-lx2160a-multicore-communications-processor:LX2160A?tab=Documentation_Tab
> Hi @Pankaj Bansal, could you please also have a check?
Can someone check the vf610, too?
regards,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
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