> -----Original Message-----
> From: Aisheng Dong
> Sent: 2019年4月29日 18:36
> To: Joakim Zhang <qiangqing.zhang@xxxxxxx>; wg@xxxxxxxxxxxxxx;
> mkl@xxxxxxxxxxxxxx; davem@xxxxxxxxxxxxx
> Cc: dl-linux-imx <linux-imx@xxxxxxx>; linux-can@xxxxxxxxxxxxxxx;
> netdev@xxxxxxxxxxxxxxx
> Subject: RE: [PATCH] can: flexcan: change .tseg1_min value to 2 in bittiming
> const
>
> > From: Joakim Zhang
> > Sent: Monday, April 29, 2019 3:48 PM
> >
> > Time Segment1(tseg1) is composed of Propagate Segment(prop_seg) and
> > Phase Segmeng1(phase_seg1). The range of Time Segment1(plus 2) is 2 up
> > to
> > 16 according to latest reference manual. That means the minimum value
> > of PROPSEG and PSEG1 bit field is 0. So change .tseg1 min value to 2.
> >
>
> I saw latest MX6Q RM still indicates it's 4-16.
> Can you help double check with IC guys whether all RM of related chips need
> update?
Okay, I referred to 2018 RM and specific RM for imx8QM/QXP. I will double check with IC guys.
Best Regards,
Joakim Zhang
> Regards
> Dong Aisheng
>
> > Signed-off-by: Joakim Zhang <qiangqing.zhang@xxxxxxx>
> > ---
> > drivers/net/can/flexcan.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
> > index
> > e35083ff31ee..2ea35ef4aa27 100644
> > --- a/drivers/net/can/flexcan.c
> > +++ b/drivers/net/can/flexcan.c
> > @@ -327,7 +327,7 @@ static const struct flexcan_devtype_data
> > fsl_ls1021a_r2_devtype_data = {
> >
> > static const struct can_bittiming_const flexcan_bittiming_const = {
> > .name = DRV_NAME,
> > - .tseg1_min = 4,
> > + .tseg1_min = 2,
> > .tseg1_max = 16,
> > .tseg2_min = 2,
> > .tseg2_max = 8,
> > --
> > 2.17.1
